In the manufacture of semiconductor devices, such as static random access memory (SRAM) devices, for example, optical lithography processes are generally employed in the formation of poly lines or gate lines (PC lines) in a polysilicon layer (or metal gate stack) which, when positioned over active regions of an underlying silicon substrate, serve as MOS transistor gates. However, optical lithography processes suffer from shortcomings (e.g. distortion of mask patterns due to light diffraction) which cause corner rounding and line-end shortening of poly lines and results in gap distances between line ends to be greater than designed. In attempts to avoid such undesirable results, optical proximity correction (OPC) is employed to compensate for diffraction and other process errors. For example, one technique to compensate for line-end shortening, line ends are extended in the optical mask which results in a poly line lengths being closer to the intended design layout. However, such line extension beyond the active areas necessitates an undesirable increase in the area required for a memory cell.
One technique employed to prevent line-end shortening and achieve small line end gaps or tip-to-tip distances without the drawbacks of line-end extension is “double patterning.” According to one double patterning technique, two separate exposures of a same photoresist layer using two different photomasks are employed. The first mask and exposure forms a pattern of poly lines in the photoresist layer in a first direction (e.g. vertical direction), while the second mask and exposure forms a plurality of small isolation segments or trenches in the photoresist layer which are perpendicular to the first direction (e.g. horizontal direction), each of which intersects at least one poly line of the pattern so as to form two line ends and the gap therebetween. According to one embodiment, the resulting pattern is etched into the polysilicon layer to form the desired poly line design.
While such double patterning techniques are work well for 45 nm node technology (i.e. the average half-pitch of a memory cell is 45 nm), the lithographic process window is nearly unmanageable for 32 nm node technology, and printing isolation segments or trenches on the order of 30 nm for 22 nm node technology with sufficient lithogrpahic process margins is not possible with 1.35 NA (numerical aperture) immersion lithography.
For these and other reasons, there is a need for the present invention.